I2C - Revision history

Savoundg at 20:18, 7 October 2017

2017-10-07T20:18:42Z

← Older revision		Revision as of 20:18, 7 October 2017
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	I2C address ~~slave~~ 7-bit		The I2C slave address is coded on 7-bit and is shifted to the left for 1 bit to code the read-write (RW) bit.
			{\| class="wikitable"
			!Operation
			!RW
			\|-
			\|Write
			\|0
			\|-
			\|Read
			\|1
			\|}
	addr << 1 \| RW		addr << 1 \| RW

	~~RW=1 (0=WRITE, 1=READ)~~

	Start: A high-to-low transition of SDA with SCL high		Start: A high-to-low transition of SDA with SCL high
Line 9:		Line 16:
	Stop: A low-to-high transition of SDA with SCL high		Stop: A low-to-high transition of SDA with SCL high

	Acknowledge (ACK): On the ninth clock cycle after every address or data byte is transferred, the receiver		Acknowledge (ACK): On the ninth clock cycle after every address or data byte is transferred, the receiver will pull the SDA pin low to acknowledge proper reception of the byte.

	will pull the SDA pin low to acknowledge proper reception of the byte.

	~~Not Acknowledge (NOT ACK): Alternatively, on the ninth clock cycle after every address or data byte is~~

	~~transferred, the receiver can leave the SDA pin high to indicate that there was a problem with the reception~~

	of the byte or that this byte completes the group transfer.		Not Acknowledge (NOT ACK): Alternatively, on the ninth clock cycle after every address or data byte is transferred, the receiver can leave the SDA pin high to indicate that there was a problem with the reception of the byte or that this byte completes the group transfer.

	== Resources ==		== Resources ==

2017-06-02T22:52:03Z

← Older revision		Revision as of 22:52, 2 June 2017
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	addr << 1 \| RW		addr << 1 \| RW

	RW=1		RW=1 (0=WRITE, 1=READ)

	Start: A high-to-low transition of SDA with SCL high		Start: A high-to-low transition of SDA with SCL high

2017-06-02T21:42:00Z

← Older revision		Revision as of 21:42, 2 June 2017
Line 4:		Line 4:

	RW=1		RW=1

			Start: A high-to-low transition of SDA with SCL high

			Stop: A low-to-high transition of SDA with SCL high

			Acknowledge (ACK): On the ninth clock cycle after every address or data byte is transferred, the receiver

			will pull the SDA pin low to acknowledge proper reception of the byte.

			Not Acknowledge (NOT ACK): Alternatively, on the ninth clock cycle after every address or data byte is

			transferred, the receiver can leave the SDA pin high to indicate that there was a problem with the reception

			of the byte or that this byte completes the group transfer.

	== Resources ==		== Resources ==

2017-02-25T01:48:27Z

← Older revision		Revision as of 01:48, 25 February 2017
Line 5:		Line 5:
	RW=1		RW=1

	http://www.nxp.com/documents/user_manual/UM10204.pdf		== Resources ==
			{\| class="wikitable"
	http://www.ovt.com/download_document.php?type=document&DID=63		!
			!
			\|-
			\|I2C specification
			\|http://www.nxp.com/documents/user_manual/UM10204.pdf
			\|-
			\|SCCB specification
			\|http://www.ovt.com/download_document.php?type=document&DID=63
			\|}

2017-02-23T19:31:30Z

← Older revision		Revision as of 19:31, 23 February 2017
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	http://www.nxp.com/documents/user_manual/UM10204.pdf		http://www.nxp.com/documents/user_manual/UM10204.pdf

			http://www.ovt.com/download_document.php?type=document&DID=63

2017-02-20T19:24:03Z

← Older revision		Revision as of 19:24, 20 February 2017
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	RW=1		RW=1

			http://www.nxp.com/documents/user_manual/UM10204.pdf

2016-08-11T18:21:27Z

Created page with "I2C address slave 7-bit addr << 1 | RW RW=1"

New page

I2C address slave 7-bit

addr << 1 | RW

RW=1