U-Boot: Difference between revisions
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| Line 5: | Line 5: | ||
{| class="wikitable" | {| class="wikitable" | ||
!Instruction | !Instruction | ||
! | !Description | ||
!Command cycle | !Command cycle | ||
!Bitlen | !Bitlen | ||
| Line 20: | Line 20: | ||
|- | |- | ||
|RDSR | |RDSR | ||
| | |Read the Status Register | ||
|05H | |05H | ||
|16 | |16 | ||
|p. 10 | |p. 10 | ||
|U-Boot > sspi 0x7100 16 | |U-Boot > sspi 0x7100 16 0500 | ||
0002 | |||
|- | |- | ||
|RDCR | |RDCR | ||
| | | | ||
Read the Configuration Register | |||
|35H | |35H | ||
|16 | |16 | ||
| | | | ||
| | |U-Boot > sspi 0x7100 16 3500 | ||
0008 | |||
|- | |- | ||
|WREN | |WREN | ||
| | |Write-Enable: required for ULBPR, PP, ... | ||
|06H | |06H | ||
|8 | |8 | ||
| Line 43: | Line 47: | ||
|- | |- | ||
|WBPR | |WBPR | ||
| | |Write Block-Protection Register | ||
|42H | |42H | ||
|152 | |152 | ||
| | |p. 36 | ||
| | |U-Boot > sspi 0x7100 8 06 | ||
00 | |||
U-Boot > sspi 0x7100 152 42000000000000000000000000000000000000 | |||
00000000000000000000000000000000000000 | |||
|- | |- | ||
|RBPR | |RBPR | ||
| | |Read Block-Protection Register | ||
|72H | |72H | ||
|152 | |152 | ||
| | |p. 35 | ||
| | |U-Boot > sspi 0x7100 152 72000000000000000000000000000000000000 | ||
00FFFFFFFFFFFFFFFFFFFF0000000000000000 | |||
|- | |- | ||
|ULBPR | |ULBPR | ||
| | |Global Block-Protection Unlock | ||
|98H | |98H | ||
|8 | |8 | ||
| | |p. 39 | ||
| | |U-Boot > sspi 0x7100 8 06 | ||
00 | |||
U-Boot > sspi 0x7100 8 98 | |||
00 | |||
|- | |- | ||
|Read (40MHz) | |Read (40MHz) | ||
| | | | ||
|03H | |03H | ||
| | |N/A | ||
|p. 15 | |p. 15 | ||
|Read at offset 0 32 bits | |Read at offset 0 32 bits | ||
U-Boot > sspi 0x7100 64 0300000000000000 | U-Boot > sspi 0x7100 64 0300000000000000 | ||
00000000FFFFFFFF | 00000000FFFFFFFF | ||
|- | |- | ||
| Line 76: | Line 92: | ||
|20H | |20H | ||
|32 | |32 | ||
| | |||
| | |||
|- | |||
|PP | |||
|Page Program | |||
|02H | |||
|N/A | |||
| | | | ||
| | | | ||
|} | |} | ||
Revision as of 21:12, 19 May 2016
U-Boot is a bootloader.
Communicate with the SST26VF032B
| Instruction | Description | Command cycle | Bitlen | Source | Example |
|---|---|---|---|---|---|
| JEDEC-ID | 9FH | 32 | U-Boot > sspi 0x7100 32 9f000000
00BF2642 | ||
| RDSR | Read the Status Register | 05H | 16 | p. 10 | U-Boot > sspi 0x7100 16 0500
0002 |
| RDCR |
Read the Configuration Register |
35H | 16 | U-Boot > sspi 0x7100 16 3500
0008 | |
| WREN | Write-Enable: required for ULBPR, PP, ... | 06H | 8 | p. 33 | U-Boot > sspi 0x7100 8 06
00 |
| WBPR | Write Block-Protection Register | 42H | 152 | p. 36 | U-Boot > sspi 0x7100 8 06
00 U-Boot > sspi 0x7100 152 42000000000000000000000000000000000000 00000000000000000000000000000000000000 |
| RBPR | Read Block-Protection Register | 72H | 152 | p. 35 | U-Boot > sspi 0x7100 152 72000000000000000000000000000000000000
00FFFFFFFFFFFFFFFFFFFF0000000000000000 |
| ULBPR | Global Block-Protection Unlock | 98H | 8 | p. 39 | U-Boot > sspi 0x7100 8 06
00 U-Boot > sspi 0x7100 8 98 00 |
| Read (40MHz) | 03H | N/A | p. 15 | Read at offset 0 32 bits
U-Boot > sspi 0x7100 64 0300000000000000 00000000FFFFFFFF | |
| SE | Sector-Erase (change to 1) a 4KiB sector | 20H | 32 | ||
| PP | Page Program | 02H | N/A |